GVSOC developer documentation

This documentation is designed to assist GVSOC users in developing their own models.

It aims to help users:

• Understand the programming model employed for developing GVSOC models.

• Perform architecture exploration.

• Create peripheral models to enable full-board simulation.

• Enhance or fine-tune existing models.

• Component model
  • High-level component model
  • Python generators
  • C++ component model
• Block object
  • Overview
  • Lifecycle methods
  • Event-based modeling
  • Clock model
  • Asynchronous blocks
• GVSOC architecture
  • Overview
  • Code organization
• Interfaces
  • Memory-mapped IO request
• Models
  • Utility blocks
  • ISS
  • L1 interconnect
  • Converter
• Tutorials
  • 0 - How to build a system from scratch
  • 1 - How to write a component from scratch
  • 2 - How to make components communicate together
  • 3 - How to add system traces to a component
  • 4 - How to add VCD traces to a component
  • 5 - How to add a register map in a component
  • 6 - How to add timing
  • 7 - How to use the IO request interface
  • 8 - How to add mutiple cores
  • 9 - How to handle clock domains and frequency scaling
  • 10 - How to customize an interconnect timing
  • 11 - How to add an ISS instruction
  • 12 - How to time an ISS instruction
  • 13 - How to add an ISS isa
  • 14 - How to add power traces to a component
  • 15 - How to build a multi-chip system
  • 16 - How to control GVSOC from a python script
  • 17 - How to control GVSOC from an external simulator
  • 18 - How to boot Linux
  • 19 - How to test a model with a standalone testbench
  • 20 - How to model a UART peripheral

Indices and tables

• Index

• Module Index

• Search Page